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19-5331; Rev 0; 6/10
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
General Description
The MAX5974_ provide control for wide-input-voltage, active-clamped, current-mode PWM, forward converters in Power-over-Ethernet (PoE) powered device (PD) applications. The MAX5974A/MAX5974C are well-suited for universal or telecom input range, while the MAX5974B/ MAX5974D also accommodate low input voltage down to 10.5V. The devices include several features to enhance supply efficiency. The AUX driver recycles magnetizing current instead of wasting it in a dissipative clamp circuit. Programmable dead time between the AUX and main driver allows for zero-voltage switching (ZVS). Under lightload conditions, the devices reduce the switching frequency (frequency foldback) to reduce switching losses. The MAX5974A/MAX5974B feature unique circuitry to achieve output regulation without using an optocoupler, while the MAX5974C/MAX5974D utilize the traditional optocoupler feedback method. An internal error amplifier with a 1% reference is very useful in nonisolated design, eliminating the need for an external shunt regulator. The devices feature a unique feed-forward maximum duty-cycle clamp that makes the maximum clamp voltage during transient conditions independent of the line voltage, allowing the use of a power MOSFET with lower breakdown voltage. The programmable frequency dithering feature provides low-EMI, spread-spectrum operation. The MAX5974_ are available in 16-pin TQFN-EP packages and are rated for operation over the -40C to +85C temperature range.
Features
S Peak_Current-Mode_Control,_Active-Clamped_ Forward_PWM_Controller S Regulation_Without_Optocoupler_(MAX5974A/ MAX5974B) S Internal_1%_Error_Amplifier S 100kHz_to_600kHz_Programmable_Q8%_Switching_ Frequency,_Synchronization_Up_to_1.2MHz S Programmable_Frequency_Dithering_for_Low-EMI,_ Spread-Spectrum_Operation S Programmable_Dead_Time,_PWM_Soft-Start,_ Current_Slope_Compensation S Programmable_Feed-Forward_Maximum_Duty-_ Cycle_Clamp,_80%_Maximum_Limit S Frequency_Foldback_for_High-Efficiency_LightLoad_Operation S Internal_Bootstrap_UVLO_with_Large_Hysteresis S 100A_(typ)_Startup_Supply_Current S Fast_Cycle-by-Cycle_Peak_Current-Limit,_35ns_ Typical_Propagation_Delay S 115ns_Current-Sense_Internal_Leading-Edge_ Blanking S Output_Short-Circuit_Protection_with_Hiccup_Mode S Reverse_Current_Limit_to_Prevent_Transformer_ Saturation_Due_to_Reverse_Current S 3mm_x_3mm,_Lead-Free,_16-Pin_TQFN-EP
MAX5974A/MAX5974B/MAX5974C/MAX5974D
Applications
PoE IEEE(R) 802.3af/at Powered Devices High-Power PD (Beyond the 802.3af/at Standard) Active-Clamped Forward DC-DC Converters IP Phones Wireless Access Nodes Security Cameras
Ordering Information
PART MAX5974AETE+ MAX5974BETE+** MAX5974CETE+ MAX5974DETE+** TOP_MARK +AHY +AHZ +AIA +AIB PIN-PACKAGE 16 TQFN-EP* 16 TQFN-EP* 16 TQFN-EP* 16 TQFN-EP* UVLO_THRESHOLD_(V) 20 10 20 10 FEEDBACK_MODE Sample/Hold Sample/Hold Continuously Connected Continuously Connected
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. **Future product--Contact factory for availability. IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
________________________________________________________________ _Maxim Integrated Products_ _ 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
ABSOLUTE_MAXIMUM_RATINGS
IN to GND ..............................................................-0.3V to +24V EN, NDRV, AUXDRV to GND .....................-0.3V to (VIN + 0.3V) RT, DT, FFB, COMP, SS, DCLMP, DITHER/SYNC to GND .................................................................-0.3V to +6V FB to GND (MAX5974A/MAX5974B only) ..................-6V to +6V FB to GND (MAX5974C/MAX5974D only) ..............-0.3V to +6V CS, CSSC to GND ...................................................-0.8V to +6V PGND to GND ......................................................-0.3V to +0.3V Maximum Input/Output Current (continuous) NDRV, AUXDRV ............................................................100mA NDRV, AUXDRV (pulsed for less than 100ns) .................. Q1A Continuous Power Dissipation (TA = +70NC) (Note 1) 16-Pin TQFN (derate 20.8mW/NC above +70NC) .......1666mW Junction-to-Case Thermal Resistance (BJC) (Note 1) 16-Pin TQFN...................................................................7NC/W Junction-to-Ambient Thermal Resistance (BJA) (Note 1) 16-Pin TQFN.................................................................48NC/W Operating Temperature Range .......................... -40NC to +85NC Maximum Junction Temperature.....................................+150NC Storage Temperature Range............................ -65NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC Soldering Temperature (reflow) ......................................+260NC
Note_1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL_CHARACTERISTICS
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MAX5974A/ MAX5974C MAX5974B/ MAX5974D MIN TYP MAX UNITS UNDERVOLTAGE_LOCKOUT/STARTUP_(IN) 19.1 9.4 6.65 19.8 9.8 7 20.4 V 10.25 7.35 V
Bootstrap UVLO Wakeup Level
VINUVR
VIN rising
Bootstrap UVLO Shutdown Level IN Supply Current in Undervoltage Lockout IN Supply Current After Startup ENABLE_(EN) Enable Threshold Input Current OSCILLATOR_(RT) RT Bias Voltage NDRV Switching Frequency Range NDRV Switching Frequency Accuracy Maximum Duty Cycle
VINUVF
VIN falling VIN = +18V (for MAX5974A/ MAX5974C); VIN = +9V (for MAX5974B/MAX5974D), when in bootstrap UVLO VIN = +12V VEN rising VEN falling
ISTART
100
150
FA
IC VENR VENF IEN VRT fSW
1.8 1.17 1.09 1.215 1.14
3 1.26 1.19 1
mA
V FA V
1.23 100 -8 600 +8 80 82
kHz % %
DMAX
fSW = 250kHz
79
2
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
ELECTRICAL_CHARACTERISTICS_(continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER SYNCHRONIZATION_(SYNC) Synchronization Logic-High Input Synchronization Pulse Width Synchronization Frequency Range Maximum Duty Cycle During Synchronization DITHERING_RAMP_GENERATOR_(DITHER) Charging Current Discharging Current Ramp's High Trip Point Ramp's Low Trip Point SOFT-START_AND_RESTART_(SS) Charging Current ISS-CH ISS-D Discharging Current ISS-DH VSS = 2V, normal shutdown (VEN < VENF or VIN < VINUVF), VSS = 2V, hiccup mode discharge for tRESTART (Note 3) 9.5 0.65 1.6 10 1.34 2 10.5 2 2.4 FA mA FA VDITHER = 0V VDITHER = 2.2V 45 43 50 50 2 0.4 55 57 FA FA V V fSYNCIN 1.1 x fSW VIH-SYNC 2.91 50 2x fSW V ns kHz % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5974A/MAX5974B/MAX5974C/MAX5974D
DMAX x fSYNC/ fSW
Discharge Threshold to Disable Hiccup and Restart Minimum Restart Time During Hiccup Mode Normal Operating High Voltage Duty-Cycle Control Range DUTY-CYCLE_CLAMP_(DCLMP) DCLMP Input Current Duty-Cycle Control Range NDRV_DRIVER Pulldown Impedance Pullup Impedance Peak Sink Current Peak Source Current Fall Time Rise Time
VSS-DTH tRSTRT-MIN VSS-HI VSS-DMAX IDCLMP VDCLMP-R DMAX (typ) = (VSS-DMAX/2.46V) VDCLMP = 0 to 5V VDCLMP = 0.5V DMAX (typ) = 1 - (VDCLMP/2.43V) VDCLMP = 1V VDCLMP = 2V 0 -100 73 54 14.7
0.15 1024 5 2 0 75.4 56 16.5 1.9 4.7 1 0.65 +100 77.5 58 18.3 3.4 8.3
V Clock Cycles V V nA %
RNDRV-N RNDRV-P
INDRV (sinking) = 100mA INDRV (sourcing) = 50mA
I I A A ns ns
tNDRV-F tNDRV-R
CNDRV = 1nF CNDRV = 1nF
14 27
3
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
ELECTRICAL_CHARACTERISTICS_(continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER AUXDRV_DRIVER Pulldown Impedance Pullup Impedance Peak Sink Current Peak Source Current Fall Time Rise Time DEAD-TIME_PROGRAMMING_(DT) DT Bias Voltage NDRV to AUXDRV Delay (Dead Time) VDT From NDRV falling to AUXDRV falling AUXDRV rising to NDRV rising RDT = 10kI RDT = 100kI RDT = 10kI RDT = 100kI 310 300 1.215 40 350 40 360 420 410 V ns ns tAUX-F tAUX-R CAUXDRV = 1nF CAUXDRV = 1nF RAUX-N RAUX-P IAUXDRV (sinking) = 50mA IAUXDRV (sourcing) = 25mA 4.3 10.6 0.5 0.3 24 45 7.7 18.9 I I A A ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
tDT
CURRENT-LIMIT_COMPARATORS_(CS) Cycle-by-Cycle Peak Current-Limit Threshold Cycle-by-Cycle Reverse Current-Limit Threshold Current-Sense Blanking Time for Reverse Current Limit Number of Consecutive Peak Current-Limit Events to Hiccup Current-Sense Leading-Edge Blanking Time Propagation Delay from Comparator Input to NDRV Minimum On-Time SLOPE_COMPENSATION_(CSSC) Slope Compensation Current Ramp Height PWM_COMPARATOR Comparator Offset Voltage Current-Sense Gain Current-Sense Leading-Edge Blanking Time Comparator Propagation Delay VPWM-OS ACS-PWM tCSSC-BLANK tPWM VCOMP - VCSSC DVCOMP/DVCSSC (Note 4) From NDRV rising edge Change in VCSSC = 10mV (including internal leading-edge blanking) 1.35 3.1 1.7 3.33 115 150 2 3.6 V V/V ns ns Current ramp's peak added to CSSC input per switching cycle 47 52 58 FA VCS-PEAK VCS-REV tCS-BLANKREV
375 Turns AUXDRV off for the remaining cycle if reverse current limit is exceeded From AUXDRV falling edge -118
393 -100 115 8
410 -88
mV mV ns Events ns
NHICCUP tCS-BLANK From NDRV rising edge From CS rising (10mV overdrive) to NDRV falling (excluding leading-edge blanking) 100
115
tPDCS tON-MIN
35 150 200
ns ns
4
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
ELECTRICAL_CHARACTERISTICS_(continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = +2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, CIN = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2) PARAMETER ERROR_AMPLIFIER VFB when ICOMP = 0, VCOMP = 2.5V MAX5974A/ MAX5974B MAX5974C/ MAX5974D MAX5974A/ MAX5974B MAX5974C/ MAX5974D MAX5974A/ MAX5974B MAX5974C/ MAX5974D Open loop (typical gain = 1) -3dB frequency VFB = 1V, VCOMP = 2.5V VFB = 1.75V, VCOMP = 1V MAX5974A/ MAX5974B MAX5974C/ MAX5974D 300 300 1.5 1.202 -250 -500 80 1.8 1.8 2.55 2.66 2 MHz 30 375 375 455 455 FA FA 3.2 mS 3.5 1.52 1.215 1.54 V 1.227 +250 nA +100 dB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5974A/MAX5974B/MAX5974C/MAX5974D
FB Reference Voltage
VREF
FB Input Bias Current
IFB
VFB = 0 to 1.75V
Voltage Gain
AEAMP
Transconductance
gM
Transconductance Bandwidth
BW
Source Current Sink Current FREQUENCY_FOLDBACK_(FFB) VCSAVG-to-FFB Comparator Gain FFB Bias Current NDRV Switching Frequency During Foldback IFFB fSW-FB
10 VFFB = 0V, VCS = 0V (not in FFB mode) 26 30 fSW/2 33
V/V FA kHz
Note_2: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design. Note_3: See the Output Short-Circuit Protection with Hiccup Mode section. Note_4: The parameter is measured at the trip point of latch with VFB = 0V. Gain is defined as DVCOMP/DVCSSC for 0.15V < DVCSSC < 0.25V.
5
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Typical Operating Characteristics
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.)
IN UVLO WAKE-UP LEVEL vs. TEMPERATURE
MAX5974A/B/C/D toc01
IN UVLO WAKE-UP LEVEL vs. TEMPERATURE
MAX5974A/B/C/D toc02
IN UVLO SHUTDOWN LEVEL vs. TEMPERATURE
MAX5974A/B/C/D toc03
20.1 20.0 19.9 19.8 19.7 19.6 19.5
MAX5974A/MAX5974C
10.1 10.0 9.9 9.8 9.7 9.6 9.5
MAX5974B/MAX5974D
7.3 7.2 7.1 7.0 6.9 6.8
IN UVLO WAKE-UP LEVEL (V)
IN UVLO WAKE-UP LEVEL (V)
-40
-15
10
35
60
85
-40
-15
10
35
60
IN UVLO SHUTDOWN LEVEL
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
EN RISING THRESHOLD vs. TEMPERATURE
MAX5974A/B/C/D toc04
EN FALLING THRESHOLD vs. TEMEPRATURE
1.149 EN FALLING THRESHOLD (V) 1.148 1.147 1.146 1.145 1.144 1.143
MAX5974A/B/C/D toc05
UVLO SHUTDOWN CURRENT vs. TEMPERATURE
MAX5974A/B/C/D toc06
1.220 1.218 1.216 1.214 1.212 1.210 -40 -15 10 35 60
1.150
140
EN RISING THRESHOLD (V)
UVLO CURRENT (A)
120
MAX5974A/MAX5974C
100
80
MAX5974B/MAX5974D
60 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
1.142 85 TEMPERATURE (C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5974A/MAX5974C)
MAX5974A/B/C/D toc07
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5974B/MAX5974D)
MAX5974A/B/C/D toc08
SUPPLY CURRENT vs. SWITCHING FREQUENCY
MAX5974A/B/C/D toc09
10,000
TA = +85C
10,000
2.4 2.0 SUPPLY CURRENT (mA) 1.6 1.2 0.8 0.4
TA = +85C
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
1000
1000
TA = -40C
100
100
TA = -40C
10 0 2 4 6 8 10 12 14 16 18 20 22 SUPPLY VOLTAGE (V) 10 0 2 4 6 8 10 12 14 16 18 20 22 SUPPLY VOLTAGE (V)
0 0 100 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz)
6
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.)
SOFT-START CHARGING CURRENT vs. TEMPERATURE
SOFT-START CHARGING CURRENT (A)
MAX5974A/MAX5974B/MAX5974C/MAX5974D
SWITCHING FREQUENCY vs. RRT VALUE
MAX5974A/B/C/D toc11 MAX5974A/B/C/D toc10
SWITCHING FREQUENCY vs. TEMPERATURE
251 SWITCHING FREQUENCY (kHz) 250 249 248 247 246 245
MAX5974A/B/C/D toc12
10.06 10.05 10.04 10.03 10.02 10.01 10.00 9.99 9.98 9.97 -40 -15 10 35 60
1000
252
SWITCHING FREQUENCY (kHz)
100
10 85 10 RRT VALUE (k) 100 TEMPERATURE (C)
244 -40 -15 10 35 60 85 TEMPERATURE (C)
FREQUENCY DITHERING vs. RDITHER
MAX5974A/B/C/D toc13
MAXIMUM DUTY CYCLE vs. SWITCHING FREQUENCY
MAX5974A/B/C/D toc14
MAXIMUM DUTY CYCLE vs. TEMPERATURE
80.9 MAXIMUM DUTY CYCLE (%) 80.8 80.7 80.6 80.5 80.4 80.3 80.2
MAX5974A/B/C/D toc15
14 12 FREQUENCY DITHERING (%) 10 8 6 4 2 0 300 400 500 600 700 800 900
83 82 MAXIMUM DUTY CYCLE (%) 81 80 79 78 77 76 75
81.0
1000
0
100 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz)
-40
-15
10
35
60
85
RDITHER (k)
TEMPERATURE (C)
MAXIMUM DUTY CYCLE vs. SYNC FREQUENCY
40 MAXIMUM DUTY CYCLE (%) 35 30 25 20 15 10 5 0 250 300 350 400 450 500 SYNC FREQUENCY (kHz)
MAXIMUM DUTY CYCLE vs. VSS
MAX5974A/B/C/D toc17 MAX5974A/B/C/D toc16
MAXIMUM DUTY CYCLE vs. VDCLMP
90 MAXIMUM DUTY CYCLE (%) 80 70 60 50 40 30 20 10 0
MAX5974A/B/C/D toc18
45
VSS = 0.5V
100 90 MAXIMUM DUTY CYCLE (%) 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0
100
2.5
0
0.5
1.0
1.5
2.0
2.5
VSS (V)
VDCLMP (V)
7
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.)
DEAD TIME vs. RDT VALUE
MAX5974A/B/C/D toc19
DEAD TIME vs. TEMPERATURE
MAX5974A/B/C/D toc20
PEAK CURRENT-LIMIT THRESHOLD vs. TEMPERATURE
PEAK CURRENT-LIMIT THRESHOLD (mV) 397 396 395 394 393 392 391 390 389 388 -40 -15 10 35 60 85
MAX5974A/B/C/D toc21
400 350 300 DEAD TIME (ns) 250 200 150 100 50 0 10 20 30 40 50 60 70 80
102 100 98 DEAD TIME (ns) 96 94 92 90 88
398
90 100
-40
-15
10
35
60
85
110
RDT VALUE (k)
TEMPERATURE (C)
TEMPERATURE (C)
REVERSE CURRENT-LIMIT THRESHOLD vs. TEMPERATURE
MAX5974A/B/C/D toc22
SLOPE COMPENSATION CURRENT vs. TEMPERATURE
MAX5974A/B/C/D toc23
NDRV MINIMUM ON-TIME vs. TEMPERATURE
MAX5974A/B/C/D toc24
-97 REVERSE CURRENT-LIMIT THRESHOLD (mV) -98 -99 -100 -101 -102 -103 -104 -105 -106 -107 -40 -15 10 35 60
54.0 SLOPE COMPENSATION CURRENT (mA) 53.5 53.0 52.5 52.0 51.5 51.0 50.5 50.0 -40 -15 10 35 60
170 165 160 155 150 145 140
85
NDRV MINIMUM ON-TIME (ns)
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
CURRENT-SENSE GAIN vs. TEMPERATURE
MAX5974A/B/C/D toc25
FEEDBACK VOLTAGE vs. TEMPERATURE
MAX5974A/B/C/D toc26
FEEDBACK VOLTAGE vs. TEMPERATURE
MAX5974A/B/C/D toc27
3.40 3.39 CURRENT-SENSE GAIN (V/V) 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 -40 -15 10 35 60
1.220 1.219 1.218 FEEDBACK VOLTAGE (V) 1.217 1.216 1.215 1.214 1.213 1.212 1.211 1.210
MAX5974C/MAX5974D
1.522 1.521 FEEDBACK VOLTAGE (V) 1.520 1.519 1.518 1.517 1.516 -40 -15 10 35 60
85
-40
-15
10
35
60
85
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
8
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.)
TRANSCONDUCTANCE vs. TEMPERATURE
MAX5974A/B/C/D toc28
MAX5974A/MAX5974B/MAX5974C/MAX5974D
TRANSCONDUCTANCE HISTOGRAM (MAX5974A/MAX5974B)
MAX5974A/B/C/D toc29
TRANSCONDUCTANCE HISTOGRAM (MAX5974C/MAX5974D)
MAX5974A/B/C/D toc30
3.0 2.9 TRANSCONDUCTANCE (mS) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -40 -15 10 35 60
25 20 15 10 5 0
25 20 15 10 5 0
MAX5974C/MAX5974D
N (%)
MAX5974A/MAX5974B
85
2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 2.62 2.64 TRANSCONDUCTANCE (mS)
N (%)
2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74 2.76 TRANSCONDUCTANCE (mS)
TEMPERATURE (C)
ENABLE RESPONSE
MAX5974A/B/C/D toc31
SHUTDOWN RESPONSE
VEN 2V/div VNDRV 20V/div
MAX5974A/B/C/D toc32
MAX5974C
VEN 2V/div VNDRV 10V/div
VAUXDRV 20V/div VOUT 5V/div 1ms/div 4s/div
VAUXDRV 10V/div VOUT 5V/div
SHUTDOWN RESPONSE
MAX5974A/B/C/D toc33
VSS RAMP RESPONSE
VEN 2V/div VNDRV 10V/div
MAX5974A/B/C/D toc34
VSS 2V/div
VNDRV 10V/div VAUXDRV 10V/div VOUT 5V/div 100s/div 10s/div VAUXDRV 10V/div
9
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Typical Operating Characteristics (continued)
(VIN = 12V (for MAX5974A/MAX5974C, bring VIN up to 21V for startup), VCS = VCSSC = VDITHER/SYNC = VFB = VFFB = VDCLMP = VGND, VEN = 2V, NDRV = AUXDRV = SS = COMP = unconnected, RRT = 34.8kI, RDT = 25kI, unless otherwise noted.)
VDCLMP RAMP RESPONSE NDRV 10% TO 90% RISE TIME NDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc35
MAX5974A/B/C/D toc36
MAX5974A/B/C/D toc37
VDCLMP 2V/div
27.6ns
0ns
VNDRV 10V/div VAUXDRV 10V/div
VNDRV 2V/div
VNDRV 2V/div
0ns
13.8ns
10s/div
10ns/div
10ns/div
AUXDRV 10% TO 90% RISE TIME
MAX5974A/B/C/D toc38
AUXDRV 90% TO 10% FALL TIME
MAX5974A/B/C/D toc39
PEAK NDRV CURRENT
MAX5974A/B/C/D toc40
PEAK SOURCE CURRENT 45.6ns 0ns
VAUXDRV 2V/div
VAUXDRV 2V/div
INDRV 0.5A/div
0ns
21ns PEAK SINK CURRENT
10ns/div 10ns/div 200ns/div
PEAK AUXDRV CURRENT
MAX5974A/B/C/D toc41
SHORT-CIRCUIT BEHAVIOR
MAX5974A/B/C/D toc42
PEAK SOURCE CURRENT
IAUXDRV 0.2A/div
VIN
VNDRV
PEAK SINK CURRENT
ILX
400ns/div
40ms/div
10
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Pin Configuration
TOP VIEW
AUXDRV PGND NDRV CS
MAX5974A/MAX5974B/MAX5974C/MAX5974D
12 IN 13 EN 14 DCLMP 15 SS 16
11
10
9 8 CSSC GND FB COMP
MAX5974A MAX5974B MAX5974C MAX5974D +
1 DT 2 DITHER/ SYNC 3 RT EP 4 FFB
7 6 5
THIN QFN
Pin Description
PIN 1 NAME DT FUNCTION Dead-Time Programming Resistor Connection. Connect resistor RDT from DT to GND to set the desired dead time between the NDRV and AUXDRV signals. See the Dead Time section to calculate the resistor value for a particular dead time. Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency operation, connect a capacitor from DITHER to GND and a resistor from DITHER to RT. To synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to the synchronization pulse. Switching Frequency Programming Resistor Connection. Connect resistor RRT from RT to GND to set the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the resistor value for the desired oscillator frequency. Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the output average current threshold below which the converter folds back the switching frequency to 1/2 of its original value. Connect to GND to disable frequency foldback. Transconductance Amplifier Output and PWM Comparator Input. COMP is level shifted down and connected to the inverting input of the PWM comparator.
2
DITHER/ SYNC
3
RT
4
FFB
5
COMP
11
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Pin Description (continued)
PIN 6 7 8 NAME FB GND CSSC Transconductance Amplifier Inverting Input Signal Ground Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs the amount of slope compensation. See the Programmable Slope Compensation section. Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle current limit. Peak current-limit trip voltage is 400mV and reverse current-limit trip voltage is -100mV. Power Ground. PGND is the return path for gate-driver switching currents. Main Switch Gate-Driver Output pMOS Active Clamp Switch Gate-Driver Output. AUXDRV can also be used to drive a pulse transformer for synchronous flyback application. Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efficient power supplies. When the enable input EN is used to program a UVLO level for the power source, connect a zener diode between IN and PGND to ensure that VIN is always clamped below its absolute maximum rating of 24V. Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode when the voltage on EN is below VENF. When the voltage on EN is above VENR, the device checks for other enable conditions. See the Enable Input section for more information about interfacing to EN. Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistive divider between the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum duty cycle (DMAX) of the converter inversely proportional to the input supply voltage, so that the MOSFET remains protected during line transients. Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program the soft-start period. This capacitor also determines hiccup mode current-limit restart time. A resistor from SS to GND can also be used to set the DMAX below 75%. Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. FUNCTION
9 10 11 12
CS PGND NDRV AUXDRV
13
IN
14
EN
15
DCLMP
16
SS
--
EP
12
VB POK -100mV REVERSE ILIM COMP 16 SS HICCUP LATCH QSET QCLR R VSS < 150mV 115ns BLANKING 9 CS DRIVER LOGIC REVERSE ILIM LIMIT TURNS OFF AUX IMMEDIATELY VB DEAD TIME 400mV PEAK ILIM COMP 115ns BLANKING SS VB POK NDRV BLANKING PULSE SLOPE COMPENSATION 8 CSSC S COUNT 8 EVENTS 2A 2mA 10A
VC
NDRV
11
DRIVER 1A/-0.65A
DEAD-TIME CONTROL
PGND
NDRV
VC
AUXDRV
AUXDRV
12
DRIVER 0.5A/-0.3A
DT
1
PGND
SYNC
RT FFB COMP VCSAVG R1 10X PWM COMP 2 x R1
3
OSCILLATOR
DCLMP
15 20% < DMAX < 80%
5 COMP VB 1.52V gM
VB
30A/
90A
FFB 2V/400mV
4
VB
MAX5974A MAX5974B
S/H
6 FB
50A/
-50A
13 IN THERMAL SHUTDOWN POK 5V REGULATOR VB ENABLE 14 EN 1.23V UVLO
DITHER/ SYNC
2
GND
7
LOW-POWER UVLO VINUVR = 20V (MAX5974A) VINUVR = 10V (MAX5974B) VINUVF = 7V
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Block Diagrams
PGND
10
MAX5974A/MAX5974B/MAX5974C/MAX5974D
13
MAX5974A/MAX5974B/MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
14
VB POK -100mV REVERSE ILIM COMP 16 SS HICCUP LATCH QSET DEAD-TIME CONTROL QCLR R VSS < 150mV 115ns BLANKING 9 CS DRIVER LOGIC REVERSE ILIM LIMIT TURNS OFF AUX IMMEDIATELY VB DEAD TIME 400mV PEAK ILIM COMP 115ns BLANKING SS VB POK NDRV BLANKING PULSE SLOPE COMPENSATION 8 CSSC S COUNT 8 EVENTS 2A 2mA 10A FFB COMP VCSAVG R1 gM 10X PWM COMP 2 x R1 VB 1.275V 5 COMP 2V/400mV
VC
NDRV
11
DRIVER 1A/-0.65A
PGND
NDRV
VC
AUXDRV
AUXDRV
12
DRIVER 0.5A/-0.3A
DT
1
PGND
SYNC
RT
3
OSCILLATOR
DCLMP
15 20% < DMAX < 80%
VB
30A/
90A
FFB
4
VB
MAX5974C MAX5974D
6 FB
50A/ 13 IN THERMAL SHUTDOWN POK 5V REGULATOR VB ENABLE 14 EN 1.23V UVLO
-50A
DITHER/ SYNC
2
GND
7
LOW-POWER UVLO VINUVR = 20V (MAX5974C) VINUVR = 10V (MAX5974D) VINUVF = 7V
Block Diagrams (continued)
PGND
10
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Detailed Description
The MAX5974A/MAX5974B/MAX5974C/MAX5974D are optimized for controlling a 25W to 50W active-clamped, self-driven synchronous rectification forward converter in continuous-conduction mode. The main switch gate driver (NDRV) and the active-clamped switch driver (AUXDRV) are sized to optimize efficiency for 25W design. The features-rich devices are ideal for PoE IEEE 802.3af/at-powered devices. The MAX5974A/MAX5974C offer a 20V bootstrap UVLO wake-up level with a 13V wide hysteresis. The low startup and operating currents allow the use of a smaller storage capacitor at the input without compromising startup and hold times. The MAX5974A/MAX5974C are well-suited for universal input (rectified 85V AC to 265V AC) or telecom (-36V DC to -72V DC) power supplies. The MAX5974B/MAX5974D have a UVLO rising threshold of 10V and can accomodate for low-input voltage (12V DC to 24V DC) power sources such as wall adapters. Power supplies designed with the MAX5974A/MAX5974C use a high-value startup resistor, RIN, that charges a reservoir capacitor, CIN (see the Typical Application Circuits). During this initial period, while the voltage is less than the internal bootstrap UVLO threshold, the device typically consumes only 100FA of quiescent current. This low startup current and the large bootstrap UVLO hysteresis help to minimize the power dissipation across RIN even at the high end of the universal AC input voltage (265V AC). Feed-forward maximum duty-cycle clamping detects changes in line conditions and adjusts the maximum duty cycle accordingly to eliminate the clamp voltage's (i.e., the main power FET's drain voltage) dependence on the input voltage. For EMI-sensitive applications, the programmable frequency dithering feature allows up to Q10% variation in the switching frequency. This spread-spectrum modulation technique spreads the energy of switching harmonics over a wider band while reducing their peaks, helping to meet stringent EMI goals. The devices include a cycle-by-cycle current limit that turns off the main and AUX drivers whenever the internally set threshold of 400mV is exceeded. Eight consecutive occurrences of current-limit events trigger hiccup mode, which protects external components by halting switching for a period of time (tRSTRT) and allowing the overload current to dissipate in the load and body diode of the synchronous rectifier before soft-start is reattempted. The reverse current-limit feature of the devices turns the AUX driver off for the remaining off period when VCS exceeds the -100mV threshold. This protects the transformer core from saturation due to excess reverse current under some extreme transient conditions. The advantages of current-mode control over voltagemode control are twofold. First, there is the feed-forward characteristic brought on by the controller's ability to adjust for variations in the input voltage on a cycle-by-cycle basis. Second, the stability requirements of the current-mode controller are reduced to that of a single-pole system, unlike the double pole in voltage-mode control. The devices use a current-mode control loop where the scaled output of the error amplifier (COMP) is compared to a slope-compensated current-sense signal at CSSC. The enable input EN is used to enable or disable the device. Connect EN to IN for always enabled applications. Connecting EN to ground disables the device and reduces current consumption to 100FA.
MAX5974A/MAX5974B/MAX5974C/MAX5974D
Current-Mode Control Loop
Enable Input
The enable input has an accurate threshold of 1.26V (max). For applications that require a UVLO on the power source, connect a resistive divider from the power source to EN to GND as shown in Figure 1. A zener diode between IN and PGND is required to prevent IN from exceeding its absolute maximum rating of 24V when the device is disabled. The zener diode should be inactive below the maximum UVLO rising threshold voltage VINUVR(MAX) (21V for the MAX5974A/MAX5974C and 10.5V for the MAX5974B/MAX5974D). Design the resistive divider by first selecting the value of REN1 to be on the order of 100kI. Then calculate REN2 as follows: R EN2 = REN1 VEN(MAX) VS(UVLO) - VEN(MAX)
where VEN(MAX) is the maximum enable threshold voltage and is equal to 1.26V and VS(UVLO) is the desired UVLO threshold for the power source, below which the devices are disabled. In the case where EN is externally controlled and UVLO for the power source is unnecessary, connect EN to IN and an open-drain or open-collector output as shown in Figure 2. The digital output connected to EN should be capable of withstanding IN's absolute maximum voltage of 24V.
15
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
VS
RIN IN CIN REN1
The devices have an internal bootstrap UVLO that is very useful when designing high-voltage power supplies (see the Block Diagrams). This allows the device to bootstrap itself during initial power-up. The MAX5974A/MAX5974C soft-start when VIN exceeds the bootstrap UVLO threshold of VINUVR (20V typ). Because the MAX5974B/MAX5974D are designed for use with low-voltage power sources such as wall adapters outputting 12V to 24V, they have a lower UVLO wake-up threshold of 10V. The device starts up when the voltage at IN exceeds 20V (MAX5974A/MAX5974C) or 10V (MAX5974B/ MAX5974D) and the enable input voltage is greater than 1.26V.
Bootstrap Undervoltage Lockout
MAX5974
Startup Operation
DIGITAL CONTROL
EN
N
REN2
Figure 1. Programmable UVLO for the Power Source
VS
RIN IN CIN
MAX5974
DIGITAL CONTROL
EN
During normal operation, the voltage at IN is normally derived from a tertiary winding of the transformer (MAX5974C/MAX5974D). However, at startup there is no energy being delivered through the transformer; hence, a special bootstrap sequence is required. In the Typical Application Circuits, CIN charges through the startup resistor, RIN, to an intermediate voltage. Only 100FA of the current supplied through RIN is used by the ICs, the remaining input current charges CIN until VIN reaches the bootstrap UVLO wake-up level. Once VIN exceeds this level, NDRV begins switching the n-channel MOSFET and transfers energy to the secondary and tertiary outputs. If the voltage on the tertiary output builds to higher than 7V (the bootstrap UVLO shutdown level), then startup has been accomplished and sustained operation commences. If VIN drops below 7V before startup is complete, the device goes back to low-current UVLO. In this case, increase the value of CIN in order to store enough energy to allow for the voltage at the tertiary winding to build up. While the MAX5974A/MAX5974B derive their input voltage from the coupled inductor output during normal operation, the startup behavior is similar to that of the MAX5974C/MAX5974D. A capacitor from SS to GND, CSS, programs the softstart time. VSS controls the oscillator duty cycle during
N
Soft-Start
Figure 2. External Control of the Enable Input
16
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
startup to provide a slow and smooth increase of the duty cycle to its steady-state value. Calculate the value of CSS as follows: The AUXDRV output drives an external p-channel MOSFET with the aid of a level shifter. The level shifter consists of CAUX, RAUX, and D5 as shown in the Typical Application Circuits. When AUXDRV is high, CAUX is recharged through D5. When AUXDRV is low, the gate of the p-channel MOSFET is pulled below the source by the voltage stored on CAUX, turning on the pFET. Dead time between the main and AUX output edges allow ZVS to occur, minimizing conduction losses and improving efficiency. The dead time (tDT) is applied to both leading and trailing edges of the main and AUX outputs as shown in Figure 3. Connect a resistor between DT and GND to set tDT to any value between 40ns and 400ns:
p-Channel MOSFET Gate Driver
MAX5974A/MAX5974B/MAX5974C/MAX5974D
I xt C SS = SS-CH ss 2V
where ISS-CH (10FA typ) is the current charging CSS during soft-start and tSS is the programmed soft-start time. A resistor can also be added from the SS pin to GND to clamp VSS < 2V and, hence, program the maximum duty cycle to be less than 80% (see the Duty-Cycle Clamping section). The NDRV output drives an external n-channel MOSFET. NDRV can source/sink in excess of 650mA/1000mA peak current; therefore, select a MOSFET that yields acceptable conduction and switching losses. The external MOSFET used must be able to withstand the maximum clamp voltage.
Dead Time
n-Channel MOSFET Gate Driver
R DT =
10k x t DT 40ns
BLANKING, tBLK
NDRV
AUXDRV
DEAD TIME, tDT
Figure 3. Dead Time Between AUXDRV and NDRV
17
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
The ICs' switching frequency is programmable between 100kHz and 600kHz with a resistor RRT connected between RT and GND. Use the following formula to determine the appropriate value of RRT needed to generate the desired output-switching frequency (fSW): R RT = 8.7 x 10 9 fSW
Oscillator/Switching Frequency
discharging capacitance at the FET's drain, and gatecharging current. Use a small RC network for additional filtering of the leading-edge spike on the sense waveform when needed. Set the corner frequency between 10MHz and 20MHz. After the leading-edge blanking time, the device monitors VCS for any breaches of the peak current limit of 400mV. The duty cycle is terminated immediately when VCS exceeds 400mV. The devices protect the transformer against saturation due to reverse current by monitoring the voltage across RCS while the AUX output is low and the p-channel FET is on.
where fSW is the desired switching frequency. The current-sense resistor (RCS in the Typical Application Circuits), connected between the source of the n-channel MOSFET and PGND, sets the current limit. The current-limit comparator has a voltage trip level (VCS-PEAK) of 400mV. Use the following equation to calculate the value of RCS: R CS = 400mV IPRI
Reverse Current Limit
Peak Current Limit
where IPRI is the peak current in the primary side of the transformer, which also flows through the MOSFET. When the voltage produced by this current (through the current-sense resistor) exceeds the current-limit comparator threshold, the MOSFET driver (NDRV) terminates the current on-cycle, within 35ns (typ). The devices implement 115ns of leading-edge blanking to ignore leading-edge current spikes. These spikes are caused by reflected secondary currents, current-
When the device detects eight consecutive peak currentlimit events, both NDRV and AUXDRV driver outputs are turned off for a restart period, tRSTRT. After tRSTRT, the device undergoes soft-start. The duration of the restart period depends on the value of the capacitor at SS (CSS). During this period, CSS is discharged with a pulldown current of ISS-DH (2FA typ). Once its voltage reaches 0.15V, the restart period ends and the device initiates a soft-start sequence. An internal counter ensures that the minimum restart period (tRSTRT-MIN) is 1024 clock cycles when the time required for CSS to discharge to 0.15V is less than 1024 clock cycles. Figure 4 shows the behavior of the device prior and during hiccup mode.
Output Short-Circuit Protection with Hiccup Mode
VCSBL (BLANKED CS VOLTAGE)
VCS-PEAK (400mV)
HICCUP DISCHARGE WITH ISS-DH VSS-HI SOFT-START VOLTAGE, VSS
VSS-DTH tSS tRSTRT
Figure 4. Hiccup Mode Timing Diagram 18
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
The frequency foldback threshold can be programmed from 0 to 20% of the full load current using a resistor from FFB to GND. The CS voltage is sampled during the NDRV on-time, averaged using an internal RC filter, and gained up by 10 to generate a voltage, VCSAVG. When VCSAVG falls below VFFB, the device folds back the switching frequency to 1/2 the original value to reduce switching losses and increase the converter efficiency. The new switching frequency starts at the beginning of a new cycle as shown in Figure 5. Calculate the value of RFFB as follows: R FFB = 10 x ILOAD(LIGHT) x R CS IFFB
Frequency Foldback for High-Efficiency Light-Load Operation
SS By connecting a resistor between SS and ground, the voltage at SS can be made to be lower than 2V. VSS is calculated as follows:
MAX5974A/MAX5974B/MAX5974C/MAX5974D
VSS = R SS x I SS-CH
where RSS is the resistor connected between SS and GND, and ISS-CH is the current sourced from SS to RSS (10FA typ). DCLMP To set DMAX using supply voltage feed-forward, connect a resistive divider between the supply voltage, DCLMP, and GND as shown in the Typical Application Circuits. This feed-forward duty-cycle clamp ensures that the external n-channel MOSFET is not stressed during supply transients. VDCLMP is calculated as follows: VDCLMP = R DCLMP2 x VS R DCLMP1 + R DCLMP2
where RFFB is the resistor between FFB and GND, ILOAD(LIGHT) is the current at light-load conditions that triggers frequency foldback, RCS is the value of the sense resistor connected between CS and PGND, and IFFB is the current sourced from FFB to RFFB (30FA typ). The maximum duty cycle is determined by the lowest of three voltages: 2V, the voltage at SS (VSS), and the voltage (2.43V - VDCLMP). The maximum duty cycle is calculated as: V D MAX = MIN 2.43V where VMIN = minimum (2V, VSS, 2.43V - VDCLMP).
Duty-Cycle Clamping
where RDCLMP1 and RDCLMP2 are the resistive divider values shown in the Typical Application Circuits and VS is the input supply voltage. The internal oscillator can be synchronized to an external clock by applying the clock to DITHER/SYNC directly. The external clock frequency can be set anywhere between 1.1x to 2x the internal clock frequency.
Oscillator Synchronization
VCSAVG VFFB NDRV tSW tSW x 2 tSW x 2
AUXDRV
COMP
Figure 5. Entering Frequency Foldback 19
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Using an external clock increases the maximum duty cycle by a factor equal to fSYNC/fSW. This factor should be accounted for in setting the maximum duty cycle using any of the methods described in the Duty-Cycle Clamping section. The formula below shows how the maximum duty cycle is affected by the external clock frequency: D MAX = VMIN fSYNC x 2.43V fSW compensation amplitude, which is added to the currentsense signal for stability of the peak current-mode control loop. The ramp rate of the slope compensation signal is given by:
m= R CSSC x 50A x fSW 80%
where VMIN is described in the Duty-Cycle Clamping section, fSW is the switching frequency as set by the resistor connected between RT and GND, and fSYNC is the external clock frequency.
where m is the ramp rate of the slope-compensation signal, RCSSC is the value of the resistor connected between CSSC and CS used to program the ramp rate, and fSW is the switching frequency. The MAX5974A/MAX5974B include an internal error amplifier with a sample-and-hold input. The feedback input of the MAX5974C/MAX5974D is continuously connected. The noninverting input of the error amplifier is connected to the internal reference and feedback is provided at the inverting input. High open-loop gain and unity-gain bandwidth allow good closed-loop bandwidth and transient response. Calculate the power-supply output voltage using the following equation: R + R FB2 VOUT = VREF x FB1 R FB2 where VREF = 1.52V for the MAX5974A/MAX5974B and VREF = 1.215V for the MAX5974C/MAX5974D. The amplifier's noninverting input is internally connected to a soft-start circuit that gradually increases the reference voltage during startup. This forces the output voltage to come up in an orderly and well-defined manner under all load conditions.
Error Amplifier
The switching frequency of the converter can be dithered in a range of Q10% by connecting a capacitor from DITHER/SYNC to GND, and a resistor from DITHER to RT as shown in the Typical Application Circuits. This results in lower EMI. A current source at DITHER/SYNC charges the capacitor CDITHER to 2V at 50FA. Upon reaching this trip point, it discharges CDITHER to 0.4V at 50FA. The charging and discharging of the capacitor generates a triangular waveform on DITHER/SYNC with peak levels at 0.4V and 2V and a frequency that is equal to: fTRI = 50A C DITHER x 3.2V
Frequency Dithering for SpreadSpectrum Applications (Low EMI)
Typically, fTRI should be set close to 1kHz. The resistor RDITHER connected from DITHER/SYNC to RT determines the amount of dither as follows: R RT 4 %DITHER = x 3 RDITHER where %DITHER is the amount of dither expressed as a percentage of the switching frequency. Setting RDITHER to 10 x RRT generates Q10% dither. The device generates a current ramp at CSSC such that its peak is 50FA at 80% duty cycle of the oscillator. An external resistor connected from CSSC to the CS then converts this current ramp into programmable slope-
Applications Information
The bypass capacitor at IN, CIN, supplies current immediately after the devices wake up (see the Typical Application Circuits). Large values of CIN increase the startup time, but also supply gate charge for more cycles during initial startup. If the value of CIN is too small, VIN drops below 7V because NDRV does not have enough time to switch and build up sufficient voltage across the tertiary output (MAX5974C/MAX5974D) or coupled inductor output (MAX5974A/MAX5974B), which powers the device. The device goes back into UVLO and does not start. Use a low-leakage capacitor for CIN.
Startup Time Considerations
Programmable Slope Compensation
20
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Typically, offline power supplies keep startup times to less than 500ms even in low-line conditions (85V AC input for universal offline or 36V DC for telecom applications). Size the startup resistor, RIN, to supply both the maximum startup bias of the device (100FA) and the charging current for CIN. CIN must be charged to 20V within the desired 500ms time period. CIN must store enough charge to deliver current to the device for at least the soft-start time (tSS) set by CSS. To calculate the approximate amount of capacitance required, use the following formula: IG = Q GTOT fSW (I + I )(t ) CIN = IN G SS VHYST where IIN is the ICs' internal supply current (1.8mA) after startup, QGTOT is the total gate charge for the n-channel and p-channel FETs, fSW is the ICs' switching frequency, VHYST is the bootstrap UVLO hysteresis (13V typ), and tSS is the soft-start time. RIN is then calculated as follows: RIN VS(MIN) - VINUVR I START with adequate breakdown voltages, use the maximum value of VCLAMP. VCLAMP(MAX) occurs when the input voltage is at its minimum and the duty cycle is at its maximum. VCLAMP(MAX-NORMAL) during normal operation is therefore: VCLAMP(MAX-NORMAL) = VS(MIN) NP x VO 1- N S x VS(MIN)
MAX5974A/MAX5974B/MAX5974C/MAX5974D
where VS(MIN) is the minimum voltage of the power source, NP/NS is the primary to secondary turns ratio, and VO is the output voltage. The clamp capacitor, n-channel, and p-channel FETs must have breakdown voltages exceeding this level. If feed-forward maximum duty-cycle clamp is used then: V V D MAX-FF = MIN = 1 - DCLMP 2.43 2.43 V RDCLMP2 = 1 - S x 2.43 R DCLMP1 + R DCLMP2 Therefore, VCLAMP(MAX-FF) during feed-forward maximum duty clamp is: VCLAMP(MAX-FF) = = VS
where VS(MIN) is the minimum input supply voltage for the application (36V for telecom), VINUVR is the bootstrap UVLO wake-up level (20V), and ISTART is the IN supply current at startup (150FA max). Choose a higher value for RIN than the one calculated above if a longer startup time can be tolerated in order to minimize power loss on this resistor. Traditional clamp circuits prevent transformer saturation by channeling the magnetizing current (IM) of the transformer onto a dissipative RC network. To improve efficiency, the active clamp circuit recycles IM between the magnetizing inductance and clamp capacitor. VCLAMP is given by: VCLAMP = VS 1- D
2.43 x (R DCLMP1 + R DCLMP2 ) RDCLMP2
1 - D MAX -FF
Active Clamp Circuit
The AUX driver controls the p-channel FET through a level shifter. The level shifter consists of an RC network (formed by CAUX and RAUX) and diode D5, as shown in the Typical Application Circuits. Choose RAUX and CAUX so that the time constant exceeds 100/fSW. Diode D5 is a small-signal diode with a voltage rating exceeding 25V. Additionally, CCLAMP should be chosen such that the complex poles formed with magnetizing inductance (LMAG) and CCLAMP are 2x to 4x away from the loop bandwidth: 1-D 2 L MAG x C CLAMP > 3 x fBW
where VS is the voltage of the power source and D is the duty cycle. To select n-channel and p-channel FETs
21
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Bias Circuit
Optocoupler Feedback (MAX5974C/MAX5974D) An in-phase tertiary winding is needed to power the bias circuit when using optocoupler feedback. The voltage across the tertiary VT during the on-time is: N VT = VOUT x T NS where VOUT is the output voltage and NT/NS is the turns ratio from the tertiary to the secondary winding. Select the turns ratio so that VT is above the UVLO shutdown level (7.5V max) by a margin determined by the holdup time needed to "ride through" a brownout. Coupled-Inductor Feedback (MAX5974A/MAX5974B) When using coupled-inductor feedback, the power for the devices can be taken from the coupled inductor during the off-time. The voltage across the coupled inductor, VCOUPLED, during the off-time is: N VCOUPLED = VOUT x C N During on-time, the coupled output is: N VCOUPLED-ON = -(VS x S NP
- VOUT )
NC NO
where VS is the input supply voltage. Care must be taken to ensure that the voltage at FB (equal to VCOUPLED-ON attenuated by the feedback resistive divider) is not more than 5V: VFB-ON = VCOUPLED-ON x R FB2 < 5V R FB1 + R FB2 ) (
If this condition is not met, a signal diode should be placed from GND (anode) to FB (cathode). Typically, there are two sources of noise emission in a switching power supply: high di/dt loops and high dV/dt surfaces. For example, traces that carry the drain current often form high di/dt loops. Similarly, the heatsink of the main MOSFET presents a dV/dt source; therefore, minimize the surface area of the MOSFET heatsink as much as possible. Keep all PCB traces carrying switching currents as short as possible to minimize current loops. Use a ground plane for best results. For universal AC input design, follow all applicable safety regulations. Offline power supplies can require UL, VDE, and other similar agency approvals.
Layout Recommendations
O
where VOUT is the output voltage and NC/NO is the turns ratio from the coupled output to the main output winding. Select the turns ratio so that VCOUPLED is above the UVLO shutdown level (7.5V max) by a margin determined by the holdup time needed to "ride through" a brownout. This voltage appears at the input of the devices, less a diode drop. An RC network consisting of RSNUB and CSNUB is for damping the reverse recovery transients of diode D6.
22
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Typical Application Circuits
VS 36V TO 57V CBULK 33F
MAX5974A/MAX5974B/MAX5974C/MAX5974D
L1 3.3mH RIN 100kI CIN 1F 25V
D1 NT D2 L2 6.8H D3 5V, 5A RFB1 7.5kI 1% RFB2 2.49kI 1%
RDCLMP1 30.1kI 1% RDCLMP2 750I 1% CSS 0.1F
IN EN DCLMP
NP
T1
NS
RGATE1 10I
RGATE2 10I N
COUT5 COUT1 COUT2 COUT3 COUT4 0.1F N2 5i412DP
D4 N N1 5i412DP IN N3 FDS3692 RGATE3 10I NDRV N RGATE4 10I ROPTO3 4.99kI 1% U1 FOD817CSD ROPTO1 825I 1%
SS RDT 16.9kI 1% DT CDITHER 10nF RRT 14.7kI 1%
MAX5974C MAX5974D
(OPTOCOUPLER FEEDBACK)
DITHER/ SYNC RT
CCLAMP 47nF
CCOMP1 2.2nF
RCOMP2 499I 1% CCOMP2 6.8pF
AUXDRV CAUX 47nF
P
N4 IRF6217
RFFB 10.0kI 1% FFB RG1 RG2 121kI 1% 200kI 1% FB COMP GND ROPTO2 1kI 1% PGND CSSC CS
RF 499I 1% CF 330pF D5 RCSSC 4.02kI 1% RCS 0.2I
RBIAS 4.02kI 1% CINT 0.1F RCOMP2 2.00kI 1% U2 TLV4314AIDBVT-1.24V
RAUX 10kI
23
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Typical Application Circuits (continued)
D6 RFB1 54.9kI 1% TO FB RFB2 10kI 1%
VS 36V TO 57V CBULK 33F 63V
CSNUB RSNUB 10pF 69.8I 1%
RIN 100kI CIN 1F 25V NP IN T1 NS
LCOUPLED NC NO
4 x 47F 6.3V
5V, 5A
RDCLMP1 30.1kI 1%
D3 RGATE1 10I
RGATE2 10I N N2 5i412DP
COUT1 COUT2 COUT3 COUT4
COUT5 0.1F
RDCLMP2 750I 1% CSS 0.1F RDT 16.9kI 1%
EN DCLMP
D4 N N1 5i412DP
SS
MAX5974A MAX5974B
(COUPLED INDUCTOR FEEDBACK) NDRV RGATE3 10I N3 FDS3692 N
DT CDITHER 10nF RRT 14.7kI 1% RT RFFB 10kI 1%
CCLAMP 47nF RGATE4 10I
DITHER/ SYNC
AUXDRV CAUX 47nF RF 499I 1% CS CF 330pF D5 CSSC PGND RCSSC 4.02kI 1% RCS 0.2I
P
N4 IRF6217
FFB
FB CCOMP 4.7nF RZ 2kI 1% COMP GND CINT 47nF
RAUX 10kI
24
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers
Typical Application Circuits (continued)
L1 VS NT CBULK RIN D2 D1
MAX5974A/MAX5974B/MAX5974C/MAX5974D
CIN
L2 T1 D3 NP NS RGATE1 N N2 RGATE2 COUT1 COUT2 COUT3 COUT4 RFB1
RDCLMP1 RDCLMP2
IN EN DCLMP
RFB2
D4 N N1
CSS SS RDT DT RDITHER DITHER/ SYNC RT RFFB FFB FB COMP Rz CCOMP CHF GND PGND RCS CS CSSC RCSSC D5 NDRV
MAX5974C MAX5974D
CCLAMP N N3 RGATE4 AUXDRV CAUX
CDITHER
RGATE3
RRT
P
N4
RAUX
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE_ TYPE 16 TQFN-EP PACKAGE_ CODE T1633+4 OUTLINE NO. 21-0136 LAND_ PATTERN_NO. 90-0031
25
Active-Clamped, Spread-Spectrum, Current-Mode PWM Controllers MAX5974A/MAX5974B/MAX5974C/MAX5974D
Revision History
REVISION NUMBER 0 REVISION_ DATE 6/10 Initial release DESCRIPTION PAGES_ CHANGED --
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26_____________________ ________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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